International Journal of Information and Communication Technology Research

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International Journal of Information and Communication Technology Research


Algorithm for Designing VLSI Floorplan using Planar Triangulated Graph

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Author(s) Bornali Gogoi, Bichitra Kalita
On Pages 564-572
Volume No. 2
Issue No. 7
Issue Date July, 2012
Publishing Date July, 2012
Keywords Planar Triangulated Graph (PTG), circuit dual graph, hypergraph, exterior face of a PTG, interior faces of a PTG, VLSI floorplanning, I-module, L-module, T-module, Z-module.



Abstract

Floorplanning is a very crucial step in VLSI physical design. This paper presents a simple algorithm based on the concept of Planar Triangulated Graph (PTG) to place modules of a circuit dual graph on a floorplan. This algorithm places the modules on a floorplan in either I or L shape. The exterior and interior triangles of the PTG have been used for the algorithm.

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2012 IRPN Publishers